1. Field of the Invention
The invention relates to programmable logic arrays (PLAs), and more particularly to power consumption reduction in PLAs by using recursive decomposition and clock gating of an original PLA.
2. Background Information
In modern very large scale integration (VLSI) design, programmable logic arrays (PLAs) are logic structures that are typically implemented in the design. PLAs are also currently used in many microprocessors, such as the Intel Itanium™ processor. Many of the current generation processors employ dynamic PLAs for random-logic designs.
Large PLAs consume significant power due to the charging and discharging of large amounts of capacitance almost every clock. Most of this power consumption occurs from the capacitance of the “product” wires and the diffusion of the transistors connected to them. Due to the emphasis on power consumption reduction in microprocessor designs, minimizing the frequency of charging/discharging of PLAs becomes important in reducing power consumption.
Many designers implement computer aided design (CAD) tools to help minimize PLAs. One such tool, ESPRESSO, is a popular CAD tool that is used widely by designers to minimize PLAs. ESPRESSO uses a two-level representation of a boolean function as an input, and produces an optimized equivalent representation. When ESPRESSO is applied to a set of logic equations that define the outputs as sums-of-products of the inputs, it transforms the original set of equations into a functionally equivalent set, but a set with fewer products and literals. The reduction of products and literals, when applied to PLA design, reduces the number of product wires and transistors in the circuit realization. ESPRESSO uses heuristics to compute and select prime implicants. Therefore, the output is not guaranteed to be the best possible solution. In some cases, the output will be optimal, or nearly so.
In most, however, it will only be adequate. With the result of reduction of product wires and transistors in PLA design by using ESPRESSO, a power consumption reduction is realized, but not fully optimized.